The present invention relates to a non-volatile semiconductor memory device such as a flash memory, and a method of manufacturing such a device.
FIG. 1 is a plan view of a memory cell of a conventional non-volatile semiconductor memory device. FIG. 2 is a cross sectional view taken along the line II--II in FIG. 1. FIG. 3 is a cross sectional view taken along the line III--III.
A p-type semiconductor substrate 1.1 has a narrow groove for element separation, formed in the substrate, and the groove is filled with an insulation film 1.2 (that is, STI (shallow trench isolation) structure).
In an element region surrounded by the insulation film 1.2, an n-type source-drain diffusion layer 1.7 is formed. On a channel region between the source-drain diffusion layer 1.7, a floating gate electrode 1.3 is formed via a gate insulation film 1.4. The gate insulation film 1.4 serves also as a tunnel insulation film which is a transfer path for transferring a charge (electrons) from the floating gate electrode 1.3 to the semiconductor substrate 1.1 and the source-drain diffusion layer 1.7.
On a surface of the floating gate electrode 1.3, an inter-poly insulation film 1.5 is formed. The inter-poly insulation film 1.5 contains an oxide film formed by the oxidation of the floating gate electrode (for example, polysilicon) 1.3. A control gate electrode (word line) 1.5 is formed on the inter-poly insulation film 1.5.
A memory cell of the above-described non-volatile semiconductor memory device stores a data piece ("1" or "0") on the basis of the charge (amount of electrons) in the floating gate electrode 1.3. For example, in the case where the floating gate electrode is negatively charged (e.g. "1") and the threshold voltage of the memory cell (transistor) is high, even if a predetermined potential is applied to a floating gate electrode 1.3, the memory cell is not turned on. Contrarily, in the case where the floating gate electrode is positively charged (e.g. "0") and the threshold voltage of the memory cell (transistor) is low, the memory cell is turned on when the same potential is applied.
In order to rewrite data, that is, to store a charge on the floating gate electrode 1, or extract the charge therefrom, it is necessary to change the potential of the floating gate electrode 1.3.
The potential of the floating gate electrode 1.3 is determined on the basis of, for example, the potential applied to the control gate electrode 1.6, and the electrostatic capacity between the floating gate electrode 1.3 and the control gate electrode 1.6.
In order to increase the potential of the floating gate electrode 1.3 with a smallest possible potential of the control gate electrode 1.6, the electrostatic capacity between the floating gate electrode 1.3 and the control gate electrode 1.6 should be set as high as possible.
In the conventional memory cell, the control gate electrode 1.6 is provided such as to cover, in addition to the upper surface of the floating gate electrode 1.3, also two lateral surfaces of the floating gate electrode 1.3, which are located along the direction in which the control gate electrode (word line) 1.6 extends.
More specifically, the area in which the floating gate electrode 1.3 and the control gate 1.6 face with each other is increased to increase the electrostatic capacity between the floating gate electrode 1.3 and the control gate electrode 1.6.
FIG. 4 illustrates a step of the conventional method of manufacturing a non-volatile semiconductor memory device. FIG. 5 is a cross sectional view taken along the line V--V in FIG. 4, and FIG. 6 is a cross sectional view taken along the line V--V in FIG. 4.
First, a groove is made in a p-type semiconductor substrate 1.1, and the grooves is filled with an insulation film, thus forming an element separation insulation film 1.2 having an STI structure. An element region 1.9 is defined in the region surrounded by the element separation insulation film 1.2. A silicon oxide film 1.4A is formed on the element region 1.9.
Next, a polysilicon film 1.3A is formed on an entire surface of the semiconductor substrate 1.1 by the CVD method. An n-type impurity is introduced into the polysilicon film 1.3A during or after the formation of the polysilicon film 1.3A.
Then, a slit-like opening 1.8 is made at a predetermined section of the polysilicon film 13A on the element separation insulation film 1.2.
Next, a silicon oxide film 1.5A is formed on each of the upper surface of the polysilicon film 1.3, and the portions of lateral surfaces thereof, which are situated in the opening 1.8.
Subsequently, a polysilicon film 1.6A is formed on the silicon oxide film 1.5A and on the portion of the element separation insulation film 1.2, which is located in the opening 1.8, by the CVD method. To the polysilicon film 1.6A, an n-type impurity is introduced during or after the formation of the film.
Next, a line-like resist film 2.0 is formed by the photolithographic technique such that it crosses over the opening 1.8. With use of the resist film 2.0 as a mask, the polysilicon film 1.6A, the silicon oxide film 1.5A, the polysilicon film l.3A and the silicon oxide film 1.4A are etched, thus forming a floating gate electrode and a control gate electrode.
Next, with use of the floating gate electrode and the control gate electrode as a mask, an n-type impurity is introduced into the element region by the self-alignment, thus forming a source-drain diffusion layer.
Thus, a memory cell of a non-volatile semiconductor memory device is completed.
In the memory cell of the conventional non-volatile semiconductor memory device, as shown in FIG. 3, lateral sides of the floating gate electrode 1.3, situated in the direction in which the bit line extends (that is, the column direction) are not covered by the control gate electrode 1.6.
This is because the floating gate electrode 1.3 and the control gate electrode 1.6 are formed at the same time, as described above in the manufacturing method.
Therefore, with the conventional technique, it is not possible to fully increase the electrostatic capacity between the floating gate electrode 1.3 and the control gate electrode 1.6.
Further, in the conventional manufacturing method, as shown in FIG. 7, after the formation of the floating gate electrode 1.3 and the control gate electrode 1.6, the silicon oxide film 2.1 is formed on each of the lateral surfaces of the floating gate electrode 1.3, which is situated in the source-drain diffusion layer 1.7, and the upper and lateral surfaces of the control gate electrode 1.6, by heat oxidation method.
At the same time, the edge portion of the upper surface of the floating gate electrode 1.3, and the edge portion of the lower surface of the control gate electrode 1.6 are oxidized to have the shape of a bird's beak.
In general, the oxidation of these edge portions causes a decrease or a variation in the electrostatic capacity between the floating gate electrode 1.3 and the control gate electrode 1.6, and therefore it should really be prevented.
However, in some cases, depending on the size of the element, the edge portion of the lower surface of the floating gate electrode 1.3 should preferably be oxidized actively, in order to enhance the withstand voltage between the floating gate electrode 1.3 and the source-drain diffusion layer 1.7.